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low power stereo audio codec with headphone amplifier revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1 ES8388 general description features ES8388 is a high performance, low power and low cost audio codec. it consists of 2 - ch adc, 2 - ch dac, microphone amplifier, headphone amplifier, digital sound effects, and analog mixing and gain functions. the device uses a dvanced multi - bit delta - sigma modulation technique to convert data between digital and analog. the multi - bit delta - sigma modulator s make the device with low sensitivity to clock jitter and low out of band noise . adc ? 24- bit, 8 khz to 96 khz sampling fre quency ? 95 db dynamic range, 95 db signal to noise ratio, - 85 db thd+n ? stereo or mono microphone interface with microphone amplifier ? auto level control and noise gate ? 2 - to - 1 analog input selection ? various analog input mixing and gains dac ? 24- bit, 8 khz to 9 6 khz sampling frequency ? 96 db dynamic range, 96 db signal to noise ratio, - 83 db thd+n ? 40 mw headphone amplifier, pop noise free ? headphone capless mode ? stereo enhancement ? bass and treble ? various analog output mixing and gains low power ? 1.8v to 3.3v operat ion ? 7 mw playback; 16 mw playback and record system ? i 2 c or spi uc interface ? 256fs, 384fs, usb 12 mhz or 24 mhz ? master or slave serial port ? i 2 s, left justified, dsp/pcm mode applications ordering information ? mid ? mp3, mp4, pmp ? wireless audio ? digital cam era, camcorder ? gps ? bluetooth ? portable audio devices ES8388 - 40 c ~ +85 c qfn - 28
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 2 1 block diagram ..................................................................................... 4 2 28- pin qfn and pin desc riptions .................................................... 5 3 typical application circuit ............................................................ 7 4 clock modes and samp ling frequencies .................................. 7 5 micro - controller configura tion interface ......................... 9 5.1 spi ...................................................................................................... 9 5.2 2 - wire ................................................................................................ 10 6 configuration regist er definition .......................................... 11 6.1 chip control and power management .............................................. 13 6.1.1 register 0 ? chip control 1, default 0000 0110 .......................... 13 6.1.2 register 1 ? chip control 2, default 0101 1100 .......................... 13 6.1.3 register 2 ? chip power management, defau lt 1100 0011 ......... 14 6.1.4 register 3 ? adc power management, default 1111 1100 ......... 14 6.1.5 register 4 ? dac power management, default 1 100 0000 ........ 15 6.1.6 register 5 ? chip low power 1, default 0000 0000 .................... 15 6.1.7 register 6 ? chip low power 2, default 0000 0000 .................... 15 6.1.8 register 7 ? analog voltage management, default 0111 1100 .... 15 6.1.9 register 8 ? master mode control, default 1000 0000 ............... 16 6.2 adc control ...................................................................................... 16 6.2.1 register 9 ? adc control 1, default 0000 0000 .......................... 16 6.2.2 register 10 ? adc control 2, default 0000 0000 ........................ 1 7 6.2.3 register 11 ? adc control 3, default 0000 0010 ........................ 17 6.2.4 register 12 ? adc control 4, default 0000 0000 ........................ 18 6.2.5 register 13 ? adc control 5, default 0000 0110 ........................ 18 6.2.6 register 14 ? ad c control 6, default 0011 0000 ........................ 19 6.2.7 register 15 ? adc control 7, default 0010 0000 ........................ 19 6.2.8 register 16 ? adc control 8, def ault 1100 0000 ........................ 19 6.2.9 register 17 ? adc control 9, default 1100 0000 ........................ 20 6.2.10 register 18 ? adc control 10, default 0011 1000 ...................... 20 6.2.11 register 19 ? adc control 11, default 1011 0000 ...................... 20 6.2.12 register 20 ? adc control 12, default 0011 0010 ...................... 21 6.2.13 register 21 ? adc control 13, default 0000 0110 ...................... 22 6.2.14 register 22 ? adc control 14, default 0000 0000 ...................... 22 6.3 dac control ...................................................................................... 22 6.3.1 register 23 ? dac control 1, default 0000 0000 ........................ 22 6.3.2 reg ister 24 ? dac control 2, default 0000 0110 ........................ 23 6.3.3 register 25 ? dac control 3, default 0010 0010 ........................ 23 6.3.4 register 26 ? dac c ontrol 4, default 1100 0000 ........................ 24 6.3.5 register 27 ? dac control 5, default 1100 0000 ........................ 24 6.3.6 register 28 ? dac control 6, defaul t 0000 1000 ........................ 24 6.3.7 register 29 ? dac control 7, default 0000 0000 ........................ 24 6.3.8 register 30 ? dac control 8, default 0001 1111 ........................ 25 6.3.9 register 31 ? dac control 9, default 1111 0111 ......................... 25
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 3 6.3.10 register 32 ? dac control 10, default 1111 1101 ....................... 25 6.3.11 register 33 ? dac control 11, default 1111 1111 ....................... 25 6.3.12 register 34 ? dac control 12, default 0001 1111 ...................... 25 6.3.13 register 35 ? dac control 13, default 1111 0111 ....................... 25 6.3.14 register 36 ? dac control 14, default 1111 1101 ....................... 25 6.3.15 register 37 ? dac control 15, default 1111 1111 ....................... 26 6.3.16 register 38 ? dac control 16, default 0000 0000 ...................... 26 6.3.17 register 39 ? dac control 17, default 0011 1000 ...................... 26 6.3.18 register 40 ? dac control 18, default 0010 1000 ...................... 26 6.3.19 register 41 ? dac control 19, default 0010 1000 ...................... 26 6.3.20 register 42 ? dac control 20, default 0011 1000 ...................... 26 6.3.21 regi ster 43 ? dac control 21, default 0000 0000 ...................... 27 6.3.22 register 44 ? dac control 22, default 0000 0000 ...................... 27 6.3.23 register 45 ? da c control 23, default 0000 0000 ...................... 27 6.3.24 register 46 ? dac control 24, default 0000 0000 ...................... 27 6.3.25 register 47 ? dac control 25 , default 0000 0000 ...................... 28 6.3.26 register 48 ? dac control 26, default 0000 0000 ...................... 28 6.3.27 register 49 ? dac control 27, default 00 00 0000 ...................... 28 6.3.28 register 50 ? dac control 28, default 0000 0000 ...................... 29 6.3.29 register 51 ? dac control 29, default 1010 1010 ...................... 29 6.3.30 register 52 ? dac control 30, default 1010 1010 ...................... 29 7 digital audio interface .............................................................................. 29 8 electrical character istics ........................................................ 30 8.1 absolute maximum ratings ............................................................... 30 8.2 recommended operating conditions ............................................... 31 8.3 adc analog and filter characteristics and specifications ................ 31 8.4 dac analog and filter characteristics and specifications ................ 31 8.5 power consumption characteristics ................................................. 32 8.6 serial audio port switching specifications ........................................ 32 8.7 serial control port switching specifications ...................................... 34 9 package information ...................................................................... 35 10 corpoaration informatio n ....................................................... 36
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 4 1 block diagram mic amp adc mux alc lin mux lin1 micl micl+micr lin2 se dac dacl mic amp adc mux alc rin mux rin1 micr micl+micr se dac dacr mixl + lin rin da cl dacr mixr + lin rin dacl dacr mixl mixr lout1 rout1 mixl +/ - mixr lout2 rout2 dvdd pvdd dgnd avdd agnd hpvdd hpgnd vref vmid mclk clock manager uc interface ce cclk cdata serial audio data alrck asdout dlrck dsdin sclk mux rin1 rin2 lin1- r in1 lin2- rin2 mux lin1 lin2 lin1- rin1 lin2- rin2 rin2
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 5 2 28- pin qfn and pin desc riptions cclk cdata ce nc lin1 rin1 lin2 rin2 vmid dacvr ef agnd avdd hpvdd lout2 asdout nc vref rout1 lout1 hpgnd rout2 mclk dvdd pvdd dgnd sclk dsdin lrck 8 9 10 11 12 13 14 21 20 19 18 17 16 15 28 27 26 25 24 23 22 1 2 3 4 5 6 7
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 6 ES8388 is pin and size compatible to wm8988. pin name i/o description 1 mclk i master clock 2 dvdd supply digital core supply 3 p vdd suppl y digital io supply 4 dgnd supply digital ground (return path for both dvdd and p vdd) 5 s clk i/o audio data bit clock 6 dsdin i dac audio data 7 lrck i/o audio data left and right clock 8 asdo ut o adc audio data 9 nc no connect 10 vref o d ecoupling capacitor 11 rout1 o right output 1 (line or speaker/ headphone) 12 lout 1 o left output 1 ( l ine or speaker/ headphone) 13 hpgnd supply ground for analog output drivers (lout1/2, rout1/2) 14 rout2 o right output 2 ( l ine or speaker/ headphone) 1 5 lout2 o left output 2 ( l ine or speaker/ headphone) 1 6 hpvdd supply supply for analog output drivers (lout1/2, rout1/2) 1 7 avdd supply analog supply 1 8 agnd supply analog ground 19 adc vref o d ecoupling capacitor 2 0 vmid o d ecoupling capacitor 2 1 rin2 ai right channel input 2 2 2 lin2 i left channel input 2 2 3 rin1 i right channel input 1 2 4 lin1 i left channel input 1 2 5 nc no connect 26 c e i control select or d evice address selection 27 cdata i/o control data input or output 28 cclk i control clock inpu t
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 7 3 typical application circuit 4 clock modes and samp ling frequencies according to the input serial audio data sampling frequency, the device can work in two speed modes: single speed or double speed. the ranges of the sampling frequency in these two mod es are listed in table 1. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally. lrck and sclk must be synchronously derived from the system clock with specific rates. the device can auto detect mclk/lrck ratio according to table 1. the device only support s the mclk/lrck ratios listed in table 1. the lrck/sclk ratio is normally 64. table 1 slave mode sampling frequencies and mclk /lrck ratio speed mode sampling frequency mclk /lrck ratio s ingle speed 8khz ? 50khz 256, 384, 512, 768, 1024 double speed 50khz ? 100khz 128, 192, 256, 384, 512 in master mode, lrck and sclk are derived internally from mclk. the available mclk/lrck ratios and sclk/lrck ratios are listed in table 2.
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 8 table 2 ma ster mode sampling frequencies and mclk /lrck ratio mclk clkdiv2=0 mclk clkdiv2=1 adc sample rate (alrck) adcfsratio [4:0] dac sample rate (dlrck) dacfsratio [4:0] sclk ratio normal mode 12.288 mhz 24.576mhz 8 khz (mclk/1536) 01010 8 khz (mclk/1536) 01010 mclk/6 8 khz (mclk/1536) 01010 48 khz (mclk/256) 00010 mclk/4 12 khz (mclk/1024) 00111 12 khz (mclk/1024) 00111 mclk/4 16 khz (mclk/768) 00110 16 khz (mclk/768) 00110 mclk/6 24 khz (mclk/512) 00100 24 khz (mclk/512) 00100 mclk/4 32 khz (mcl k/384) 00011 32 khz (mclk/384) 00011 mclk/6 48 khz (mclk/256) 00010 8 khz (mclk/1536) 01010 mclk/4 48 khz (mclk/256) 00010 48 khz (mclk/256) 00010 mclk/4 96 khz (mclk/128) 00000 96 khz (mclk/128) 00000 mclk/2 11.2896 mhz 22.5792mhz 8.0182 khz (mc lk/1408) 01001 8.0182 khz (mclk/1408) 01001 mclk/4 8.0182 khz (mclk/1408) 01001 44.1 khz (mclk/256) 00010 mclk/4 11.025 khz (mclk/1024) 00111 11.025 khz (mclk/1024) 00111 mclk/4 22.05 khz (mclk/512) 00100 22.05 khz (mclk/512) 00100 mclk/4 44.1 khz (mclk/256) 00010 8.0182 khz (mclk/1408) 01001 mclk/4 44.1 khz (mclk/256) 00010 44.1 khz (mclk/256) 00010 mclk/4 88.2 khz (mclk/128) 00000 88.2 khz (mclk/128) 00000 mclk/2 18.432 mhz 36.864mhz 8 khz (mclk/2304) 01100 8 khz (mclk/2304) 01100 mclk/ 6 8 khz (mclk/2304) 01100 48 khz (mclk/384) 00011 mclk/6 12 khz (mclk/1536) 01010 12 khz (mclk/1536) 01010 mclk/6 16 khz (mclk/1152) 01000 16 khz (mclk/1152) 01000 mclk/6 24 khz (mclk/768) 00110 24 khz (mclk/768) 00110 mclk/6 32 khz (mclk/57 6) 00101 32 khz (mclk/576) 00101 mclk/6 48 khz (mclk/384) 00011 8 khz (mclk/2304) 01100 mclk/6 48 khz (mclk/384) 00011 48 khz (mclk/384) 00011 mclk/6 96 khz (mclk/192) 00001 96 khz (mclk/192) 00001 mclk/3 16.9344 mhz 33.8688mhz 8.0182 khz (mclk/2 112) 01011 8.0182 khz (mclk/2112) 01011 mclk/6 8.0182 khz (mclk/2112) 01011 44.1 khz (mclk/384) 00011 mclk/6 11.025 khz (mclk/1536) 01010 11.025 khz (mclk/1536) 01010 mclk/6 22.05 khz (mclk/768) 00110 22.05 khz (mclk/768) 00110 mclk/6 44.1 khz (mclk/384) 00011 8.0182 khz (mclk/2112) 01011 mclk/6 44.1 khz (mclk/384) 00011 44.1 khz (mclk/384) 00011 mclk/6 88.2 khz (mclk/192) 00001 88.2 khz (mclk/192) 00001 mclk/3 usb mode 12 mhz 24mhz 8 khz (mclk/1500) 11011 8 khz (mclk/1500) 11011 mclk 8 khz (mclk/1500) 11011 48 khz (mclk/250) 10010 mclk 8.0214 khz (mclk/1496) 11010 8.0214 khz (mclk/1496) 11010 mclk 8.0214 khz (mclk/1496) 11010 44.118 khz (mclk/272) 10011 mclk
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 9 11.0259 khz (mclk/1088) 11001 11.0259 khz (mclk/1088) 11001 mclk 12 khz (mclk/1000) 11000 12 khz (mclk/1000) 11000 mclk 16 khz (mclk/750) 10111 16 khz (mclk/750) 10111 mclk 22.0588 khz (mclk/544) 10110 22.0588 khz (mclk/544) 10110 mclk 24 khz (mclk/500) 10101 24 khz (mclk/500) 10101 mclk 32 khz (mclk/375) 10100* 32 khz (mclk/375) 10100* mclk 44.118 khz (mclk/272) 10011 8.0214 khz (mclk/1496) 11010 mclk 44.118 khz (mclk/272) 10011 44.118 khz (mclk/272) 10011 mclk 48 khz (mclk/250) 10010 8 khz (mclk/1500) 11011 mclk 48 khz (mclk/250) 10010 48 khz (m clk/250) 10010 mclk 88.235 khz (mclk/136) 10001 88.235 khz (mclk/136) 10001 mclk 96 khz (mclk/125) 10000 96 khz (mclk/125) 10000 mclk 5 micro - controller configura tion interface the device supports standard spi and 2 - wire micro - controller configuratio n interface. external micro - controller can completely configure the device through writing to internal configuration registers. please see section 8 for the details of configuration register definition. the identical device pins are used to configure eith er spi or 2 - wire interface. in spi mode, pin ce, cclk and cdata function as spi_csn, spi_clk and spi_din. in 2 - wire mode, pin ce, cclk and cdata function as ad0 , scl and sda. to select spi mode, apply high to low transition signal to ce pin . otherwise the device will operate in 2 - wire interface mode. 5.1 spi ES8388 has a spi (serial peripheral interface) compliant synchronous serial slave controller inside the chip . it provides the ability to allow the external master spi controller to access the internal regis ters, and thus control the operations of chip . all lines on the spi bus are unidirectional: the spi_clk is generated by the master controller and is primarily used to synchronize data transfer, the spi_din line carries data from the master to the slave ; s pi_csn is generated by the master to select ES8388. the timing diagram of this interface is given in figure 1. the high to low transition at spi_csn pin indicates the spi interface selected. each write procedure contains 3 words, i.e. chip address plus r/ w bit, internal register address and internal register data. every word length is fixed at 8 bits. the input spi_din data are sampled at the rising edge of spi_clk clock. the
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 10 msb bit in each word is transferred firstly. the transfer rate can be up to 10m b ps. chip address 7 bits - 0010000 0 spi_din spi_clk spi_csn 1 r/ wb 5 6 7 8 9 14 15 16 17 22 23 ram 8 bits register data 8 bits 5.2 2 - wire the device supports standard 2 - wire micro - controller configuration interface. external micro - controller can completely configure the device through writing to internal configuration registers. 2 - wire interface i s a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 2 a and figure 2 b. data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 400 kbps. a master controller initiates the transmission by sending a ?start? signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. the chip address must be 001000x, where x equals ad0. the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the master can terminate the communication by generating a ?stop? signal, which is defined as a low - to - high transition at sda while scl is high. in 2 - wire interface mode, the registers can be written and read. the formats of ?write? and ?read? instr uctions are shown in table 1 and table 2. please note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. figure 1 spi configuration interface timing diagram ram = register address mapping
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 11 table 3 write data to register in 2 - wire interface mod e chip address r/w register address data to be written start 001000 ad0 0 ack ram ack data ack stop figure 2 a 2 - wire write timing table 4 read data from register in 2 - wire interface mode chip address r/w register address start 001000 ad0 0 a ck ram ack chip address r/w data to be read start 001000 ad0 1 ack data nack stop figure 2 b 2 - wire read timing 6 configuration regist er definition spi and 2 - wire configuration interface share the same registers because there is only one interface active at any time. there are total of 53 user programmable 8 - bit registers in this device. these registers control the operations of adc and dac. external master controller can access these registers by using the slave address specified in ram (register a ddress map) register as shown in the table 5. table 5 bit content of register address map b7 b6 b5 b4 b3 b2 b1 b0 reg. 00 scpreset lrcm dacmclk samefs seqen enref vmidsel reg. 01 lpvcmmod lpvrefbuf pdnana pdnibiasgen vrefrlo pdnvrefbuf
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 12 reg. 02 adc_ digpdn dac_digpdn adc_stm_rst dac_stm_rst adcdll_pdn dacdll_pdn adcvref_pdn dacvref_pdn reg. 03 pdnainl pdnainr pdnadcl pdnadcr pdnmicb pdnadcbiasgen flashlp int1lp reg. 04 pdndacl pdndacr lout1 rout1 lout2 rout2 reg. 05 lpdacl lpdacr lplout1 lplout2 reg. 06 lppga lplmix lpadcvrp lpdacvrp reg. 07 vsel reg. 08 msc mclkdiv2 bclk_inv bclkdiv reg. 09 micampl micampr reg. 10 linsel rinsel dssel dsr reg. 11 ds monomix tri reg. 12 datsel adclrp adcwl adcformat reg. 13 adcfsmode adcfsratio reg. 14 adc_invl adc_invr adc_hpf_l adc_hpf_r reg. 15 adcramprate adcsoftramp adcler adcmute reg. 16 ladcvol reg. 17 radcvol reg. 18 alcsel maxgain mingain reg. 19 alclvl alchld reg. 20 alcdcy alcatk reg. 21 alcmode alczc time_out win_size reg. 22 ngth ngg ngat reg. 23 daclrsw ap daclrp dacwl dacformat reg. 24 dacfsmode dacfsratio reg. 25 dacramprate dacsoftramp dacler dacmute reg. 26 dacvolumel (ldacvol) reg. 27 dacvolumer (rdacvol) reg. 28 deemphasismode dac_invl dac_invr clickfree reg. 29 zerol zeror mon o se vpp_scale reg. 30 shelving_a[29:24] reg. 31 shelving_a[23:16] reg. 32 shelving_a[15:8] reg. 33 shelving_a[7:0] reg. 34 shelving_b[29:24] reg. 35 shelving_b[23:16] reg. 36 shelving_b[15:8] reg. 37 shelving_b[7:0] reg. 38 lmixsel rmix sel reg. 39 ld2lo li2lo li2lovol reg. 40 reg. 41 reg. 42 rd2ro ri2ro ri2rovol
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 13 reg. 43 slrck lrck_sel offset_dis, mclk_dis a dc_dll_pwd d ac_dll_pwd reg. 44 offset reg. 45 vroi reg. 46 lout1vol reg. 47 rout1vo l reg. 48 lout2vol reg. 49 rout2vol reg. 50 reg. 51 hplout1_ref1 hplout1_ref2 reg. 52 spklout2_ref1 spklout2_ref2 mixer_ref1 mixer_ref2 mref1 mref2 6.1 chip control and power management 6.1.1 register 0 ? chip control 1 , default 0000 0110 bit name bit description scpreset 7 0 ? normal (default) 1 ? reset control port register to default lrcm 6 0 ? alrck disabled when both adc disabled; dlrck disabled when both dac disabled (default) 1 ? alrck and dlrck disabled when all adc and dac disabled dacmclk 5 0 ? when samefs=1, adcmclk is the chip master clock source (default) 1 ? when samefs=1, dacmclk is the chip master clock source samefs 4 0 ? adc fs differs from dac fs (default) 1 ? adc fs is the same as dac fs s eqe n 3 0 ? internal power up/do wn sequence disable (default) 1 ? internal power up/down sequence enable enref 2 0 ? disable reference 1 ? enable reference (default) vmidsel 1:0 00 ? vmid disabled 01 ? 50 k ? divider enabled 10 ? 500 k ? divider enabled (default) 11 ? 5 k ? divider enable d 6.1.2 register 1 ? chip control 2, default 0 1 01 1100 bit name bit description lpvcmmod 5 0 ? normal (default) 1 ? low power lpvrefbuf 4 0 ? normal 1 ? low power (default) p dnana 3 0 ? normal 1 ? entire analog power down (default) p dni biasgen 2 0 ? norm al
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 14 1 ? ibiasgen power down (default) v reflo 1 0 ? normal (default) 1 ? low power p dnvrefbuf 0 0 ? normal (default) 1 ? power down 6.1.3 register 2 ? chip power management, default 1100 0011 bit name bit description adc_digpdn 7 0 ? normal 1 ? resets adc d em, filter and serial data port (default) da c_digpdn 6 0 ? normal 1 ? resets da c dsm, dem, filter and serial data port (default) adc_stm_rst 5 0 ? normal (default) 1 ? reset adc state machine to power down state dac_stm_rst 4 0 ? normal (default) 1 ? reset da c state machine to power down state adc d ll_pdn 3 0 ? normal (default) 1 ? adc_dll power down , stop adc clock dac dll _pdn 2 0 ? normal (default) 1 ? dac dll power down, stop dac clock adcvref_pdn 1 0 ? adc analog reference power up 1 ? adc analog reference power down (default) dacvref_pdn 0 0 ? dac analog reference power up 1 ? dac analog reference power down (default) 6.1.4 register 3 ? adc power management, default 1111 1100 bit name bit description p dn ainl 7 0 ? normal 1 ? left analog input power down (default) p dn ainr 6 0 ? normal 1 ? right analog input power down (default) p dn adcl 5 0 ? left adc power up 1 ? left adc power down (default) p dn adcr 4 0 ? right adc power up 1 ? right adc power down (default) p dn micb 3 0 ? microphone bias power o n 1 ? microphone bias power down (high impedance output, default) p dnadcbiasgen 2 0 ? normal 1 ? power down (default) flashlp 1 0 ? normal (default) 1 ? flash adc low power int1lp 0 0 ? normal (default) 1 ? int1 low power
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 15 6.1.5 register 4 ? dac power mana gement, default 1100 0000 bit name bit description p dn dacl 7 0 ? left dac power up 1 ? left dac power down (default) p dn dacr 6 0 ? right dac power up 1 ? right dac power down (default) lout1 5 0 ? lout1 disabled (default) 1 ? lout1 enabled rout1 4 0 ? rout1 disabled (default) 1 ? rout1 enabled lout2 3 0 ? lout2 disabled (default) 1 ? lout2 enabled rout2 2 0 ? rout2 disabled (default) 1 ? rout2 enabled 6.1.6 register 5 ? chip low power 1 , default 0000 0000 bit name bit description lpdacl 7 0 ? normal (d efault) 1 ? low power lpdacr 6 0 ? normal (default) 1 ? low power lplout1 5 0 ? normal (default) 1 ? low power lplout2 3 0 ? normal (default) 1 ? low power 6.1.7 register 6 ? chip low power 2 , default 0000 0000 bit name bit description lppga 7 0 ? normal (default) 1 ? low power lplmix 6 0 ? normal (default) 1 ? low power lpadcvrp 1 0 ? normal (default) 1 ? low power lpdacvrp 0 0 ? normal (default) 1 ? low power 6.1.8 register 7 ? a nalog voltage management, default 0111 1100 bit name bit description vsel 6 :0 111110 0 ? normal (default)
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 16 6.1.9 register 8 ? master mode control , default 1000 0000 bit name bit description ms c 7 0 ? slave s erial port mode 1 ? master s erial port mode (default) mclkdiv2 6 0 ? mclk not divide (default) 1 ? mclk divide by 2 bclk_inv 5 0 ? normal (default) 1 ? bclk inverted bclkdiv 4: 0 0000 0 ? master mode bclk generated automatically based on the clock table (default) 00001 ? mclk/1 00010 ? mclk/2 00011 ? mclk/3 00100 ? mclk/4 00101 ? mclk/6 00110 ? mclk/8 00111 ? mclk/9 01000 ? mclk/1 1 01001 ? mclk/12 01010 ? mclk/16 01011 ? mclk/18 01100 ? mclk/22 01101 ? mclk/24 01110 ? mclk/33 01111 ? mclk/36 10000 ? mclk/44 10001 ? mclk/48 10010 ? mclk/66 10011 ? mclk/72 10100 ? mclk/5 10101 ? mclk/10 10110 ? mclk/15 10111 ? mclk/17 11000 ? mclk/20 11001 ? mclk/25 11010 ? mclk/30 11011 ? mclk/32 11100 ? mclk/34 o thers ? mclk/4 6.2 adc control 6.2.1 register 9 ? adc control 1, default 0000 0000 bit name bit description
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 17 micampl 7:4 left channel pga gain 0000 ? 0 db ( default ) 0 001 ? + 3 db 0010 ? + 6 db 0011 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0110 ? + 18 db 0111 ? + 21 db 1000 ? + 24 db micampr 3:0 right channel pga gain 0000 ? 0db ( default ) 0 001 ? + 3 db 0010 ? + 6 db 0011 ? + 9 db 0 100 ? + 12 db 0101 ? + 15 db 0110 ? + 18 db 0111 ? + 21 db 1000 ? + 24 db 6.2.2 register 10 ? adc control 2, default 0000 0000 bit name bit description linsel 7:6 left channel input select 00 ? linput1 ( default ) 01 ? linput2 10 ? reserved 11 ? l - r differential (either linput1 - rinput1 or linput2 - rinput2, selected by ds) rinsel 5:4 right channe l input select 00 ? rinput1 ( default ) 01 ? rinput2 10 ? reserved 11 ? l - r differential (either linput1 - rinput1 or linput2 - rinput2, selected by ds) dssel 3 0 ? use one ds reg11[7] ( default ) 1 ? dsl=reg11[7], dsr=reg10[2] dsr 2 differential input select 0 ? linput1 - rinput1 (default) 1 ? linput2 - rinput2 6.2.3 register 11 ? adc control 3 , default 0000 0 0 10 bit name bit description ds 7 differential input select 0 ? linput1 - rinput1 (default)
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 18 1 ? linput2 - rinput2 monomix 4:3 00 ? stereo (default) 01 ? analog mono mix to left adc 10 ? analog mono mix to right adc 11 ? reserved tri 2 0 ? asdout is adc normal output (default) 1 ? asdout tri - stated , alrc k , dlrc k and sclk are inputs 6.2.4 register 12 ? adc control 4 , default 0000 0000 bit name bit description datsel 7:6 00 ? left data = left adc, right data = right adc 01 ? left data = left adc, right data = left adc 10 ? left data = right adc, right data = right adc 11 ? left data = right adc, right data = left adc adclrp 5 i2s, left justified or right justified mode : 0 ? left and right normal polarity 1 ? left and right invert ed polarity dsp /pcm mode : 0 ? msb is available on 2nd bclk rising edge after a lrc k rising edge 1 ? msb is available on 1st bclk rising edge after a lrc k rising edge adcwl 4:2 000 ? 24 - bit serial a udio data word length 001 ? 20 - bit serial audio data word length 010 ? 18 - bit serial audio data word length 011 ? 16 - bit serial audio data word length 100 ? 32 - bit serial audio data word length adcformat 1:0 00 ? i2s serial audio data format 01 ? left jus tify serial audio data format 10 ? right justify serial audio data format 11 ? dsp /pcm mode serial audio data format 6.2.5 register 13 ? adc control 5 , default 0000 0110 bit name bit description adc fsmode 5 0 ? single speed mode (default) 1 ? double speed mo de adcfsratio 4 : 0 m aster mode adc mclk to sampling frequency ratio
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 19 00000 ? 128 00001 ? 192 00010 ? 256 00011 ? 384 00100 ? 512 00101 ? 576 00110 ? 768 (default) 00111 ? 1024 01000 ? 1152 01001 ? 1408 01010 ? 1536 01011 ? 2112 01100 ? 2304 10000 ? 125 1 0001 ? 136 10010 ? 250 10011 ? 272 10100 ? 375 10101 ? 500 10110 ? 544 10111 ? 750 11000 ? 1000 11001 ? 1088 11010 ? 1496 11011 ? 1500 other ? reserved 6.2.6 register 14 ? adc control 6 , default 0011 0000 bit name bit description adc_invl 7 0 ? normal ( default) 1 ? left channel polarity inverted adc_invr 6 0 ? normal (default) 1 ? right channel polarity inverted a dc_ hpf _l 5 0 ? disable adc left channel high pass filter 1 ? enable adc left channel high pass filter (default) adc_ hpf _r 4 0 ? disable adc right channel high pass filter 1 ? enable adc right channel high pass filter (default) 6.2.7 register 15 ? adc control 7 , default 001 0 0000 bit name bit description adcramprate 7:6 00 ? 0.5 db per 4 lrck digital volume control ramp rate (default) 01 ? 0.5 d b per 8 lrck digital volume control ramp rate 10 ? 0.5 db per 16 lrck digital volume control ramp rate 11 ? 0.5 db per 32 lrck digital volume control ramp rate adcsoftramp 5 0 ? disabled digital volume control soft ramp 1 ? enabled digital volume control soft ramp (default) adcler 3 0 ? normal (default) 1 ? both channel gain control is set by adc left gain control register adcmute 2 0 ? normal (default) 1 ? mute adc digital output 6.2.8 register 16 ? adc control 8 , default 1100 0000 bit name bit description ladcvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 20 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.2.9 register 17 ? adc control 9 , default 1100 0000 bit name bit description radcvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.2.10 register 18 ? adc control 10 , default 0011 1000 bit name bit description alcsel 7:6 00 ? alc off 01 ? alc right channel only 10 ? alc left channel only 11 ? alc stereo maxgain 5:3 set maximum gain of pga 000 ? - 6.5 db 001 ? - 0.5 db 010 ? 5.5 db 011 ? 11.5 db 100 ? 17.5 db 101 ? 23.5 db 110 ? 29.5 db 111 ? 35.5 db mingain 2 :0 set minimum gain of pga 000 ? - 12 db 001 ? - 6 db 010 ? 0 db 011 ? +6 db 100 ? +12 db 101 ? +18 db 110 ? +24 db 111 ? +30 db 6.2.11 register 19 ? adc control 11 , default 1011 0000 bit name bit description alcl vl 7:4 alc target 0000 ? - 16.5 db
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 21 0001 ? - 15 db 0010 ? - 13.5 db ?? 0111 ? - 6 db 1000 ? - 4.5 db 1001 ? - 3 db 1010 - 1111 ? - 1.5 db alc hld 3:0 alc hold time before gain is increased 0000 ? 0ms 0001 ? 2.67ms 0010 ? 5.33ms ?? (time doubles with every step) 1001 ? 0.68s 1 010 or higher ? 1.36 s 6.2.12 register 20 ? ad c control 12 , default 0011 0010 bit name bit description alc dcy 7:4 alc decay (gain ramp up) time, a lc mode / limiter mode: 0000 ? 410 us / 90.8 us 0001 ? 820 us / 182us 0010 ? 1.64 ms / 363us ?? (time doubles with every step) 1001 ? 210 ms/46.5 ms 1010 or highe r ? 420 ms/93 ms alc atk 3:0 alc attack (gain ramp down) time, a lc mode / limiter mode: 0000 ? 104 us/ 22.7 us 0001 ? 208 us/ 45.4 u s 0010 ? 416 us/ 90.8 u s ?? (time doubles with very step) 1001 ? 53.2 ms/ 11.6 ms 1010 or higher ? 106 ms/ 23.2 ms
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 22 6.2.13 register 21 ? adc control 1 3 , default 0000 0110 6.2.14 register 22 ? adc control 1 4 , default 0000 0000 bit name bit description ngth 7:3 noise gate threshold 00000 ? - 76.5 dbfs 00001 ? - 75 dbfs ?? 11110 ? - 31.5 dbfs 11111 ? - 30 dbfs ngg 2:1 noise gate type x0 ? pga gain held constant 01 ? mute adc output 11 ? reserved ngat 0 noise gate function enable 0 ? disable 1 ? enable 6.3 dac control 6.3.1 register 23 ? dac control 1, default 0 000 0000 bit name bit description daclrswap 7 0 ? normal 1 ? left and right channel data swap daclrp 6 i2s, left justified or right justified mode : 0 ? left and right normal polarity 1 ? left and right invert ed polarity bit name bit description alcmode 7 determines the alc mode of operation: 0 ? alc mode (normal operation) 1 ? limiter mode. alczc 6 alc uses zero cross detection circuit. 0 ? d isable (recommended) 1 ? e nable time_out 5 zero cross time out 0 ? disable (default) 1 ? enable win_size 4:0 windows s ize for peak detector set the window size to n*16 samples 00110 ? 96 samples (default) 00111 ? 102 samples ? .. 11111 ? 496 samples
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 23 dsp /pcm mode : 0 ? msb is availabl e on 2nd bclk rising edge after a lrc k rising edge 1 ? msb is available on 1st bclk rising edge after a lrc k rising edgelrck polarity dacwl 5 : 3 000 ? 24 - bit serial audio data word length 001 ? 20 - bit serial audio data word length 010 ? 18 - bit serial audio d ata word length 011 ? 16 - bit serial audio data word length 100 ? 32 - bit serial audio data word length dacformat 2 : 1 00 ? i2s serial audio data format 01 ? left justify serial audio data format 10 ? right justify serial audio data format 11 ? dsp /pcm mode serial audio data format 6.3.2 register 24 ? dac control 2, default 0000 0110 bit name bit description dac fsmode 5 0 ? single speed mode (default) 1 ? double speed mode da cfsratio 4 : 0 m aster mode dac mclk to sampling frequency ratio 00000 ? 128; 00001 ? 192; 00010 ? 256; 00011 ? 384; 00100 ? 512; 00101 ? 576; 00110 ? 768; (default) 00111 ? 1024; 01000 ? 1152; 01001 ? 1408; 01010 ? 1536; 01011 ? 2112; 01100 ? 2304; 10000 ? 125; 10001 ? 136; 10010 ? 250; 10011 ? 272; 10100 ? 375; 10101 ? 500; 10110 ? 544; 10111 ? 750; 11000 ? 1000; 11001 ? 1088; 11010 ? 1496; 11011 ? 1500; other ? reserved. 6.3.3 register 25 ? dac control 3 , default 001 0 0010 bit name bit description dacramprate 7:6 00 ? 0.5 db per 4 lrck digital volume control ramp rate (default) 01 ? 0 .5 db per 32 lrck digital volume control ramp rate 10 ? 0.5 db per 64 lrck digital volume control ramp rate 11 ? 0.5 db per 128 lrck digital volume control ramp rate dacsoftramp 5 0 ? disabled digital volume control soft ramp 1 ? enabled digital volume c ontrol soft ramp (default) dacler 3 0 ? normal (default) 1 ? both channel gain control is set by dac left gain control register
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 24 dacmute 2 0 ? normal (default) 1 ? mute analog outputs for both channels 6.3.4 register 26 ? dac control 4, default 1100 0000 bit name bit description ldacvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.3.5 register 27 ? dac control 5 , default 1100 0000 bit n ame bit description rdacvol 7:0 digital volume control attenuates the signal in 0.5 db incremental from 0 to ? 96 db. 00000000 ? 0 db 00000001 ? - 0.5 db 00000010 ? - 1 db ? 11000000 ? - 96 db (default) 6.3.6 register 28 ? dac control 6 , default 0000 1000 bit na me bit description deemphasismode (deemp) 7:6 00 ? de- emphasis frequency disabled (default) 01 ? 32 khz de - emphasis frequency in single speed mode 10 ? 44.1 khz de - emphasis frequency in single speed mode 11 ? 48 khz de - emphasis frequency in single speed mode dac_invl 5 0 ? normal dac left channel analog output no phase inversion (default) 1 ? normal dac left channel analog output 180 degree phase inversion dac_invr 4 0 ? normal dac right channel analog output no phase inversion (default) 1 ? normal dac right analog output 180 degree phase inversion clickfree 3 0 ? disable digital click free power up and down 1 ? enable digital click free power up and down (default) 6.3.7 register 29 ? dac control 7 , default 0000 0 000 bit name bit description zerol 7 0 ? normal (default) 1 ? set l eft channel dac output all zero zeror 6 0 ? normal (default) 1 ? set right channel dac output all zero m ono 5 0 ? stereo (default) 1 ? mono (l+r)/2 into dacl and dacr s e 4:2 se strength
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 25 000 ? 0 (default) ?? 111 ? 7 vpp_scale 1 : 0 00 ? vpp set at 3.5v (0.7 modulation index) (default) 01 ? vpp set at 4.0v 10 ? vpp set at 3.0v 11 ? vpp set at 2.5v 6.3.8 register 30 ? dac control 8 , default 0001 1111 bit name bit description shelving _a[29:24] 5 : 0 30- bit a coefficient for shelving fil ter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.9 register 31 ? dac control 9 , default 1111 0111 bit name bit description shelving _a[23:16] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.10 register 32 ? dac control 10 , default 1111 1101 bit name bit description shelving _a[15:8] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.11 register 33 ? dac control 11 , default 1111 1111 bit name bit description shelving _a[7:0] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.12 register 34 ? dac control 12 , default 0001 1111 bit name bit description shelving _b[29:24] 5 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.13 register 35 ? dac control 13 , default 1111 0111 bit name bit description shelving _b[23:16] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.14 register 36 ? dac control 14 , default 1111 1101 bit name bit description shelving _b[15:8] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 26 6.3.15 register 37 ? dac c ontrol 15 , default 1111 1111 bit name bit description shelving _b[7:0] 7 : 0 30- bit a coefficient for shelving filter d efault value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} 6.3.16 register 38 ? dac control 16 , default 0000 0000 bit name bit description lm ixsel 5:3 left input select for output mix 000 ? lin1 ( default ) 001 ? lin2 010 ? reserved 011 ? left adc input (after mic amplifier) rmixsel 2:0 right input select for output mix 000 ? rin1 ( default ) 001 ? rin2 010 ? reserved 011 ? right adc input (after mic amplifier) 6.3.17 register 39 ? dac control 17 , default 0011 1000 bit name bit description ld2lo 7 0 ? left dac to left mixer disable (default) 1 ? left dac to left mixer enable li2lo 6 0 ? lin signal to left mixer disable (default) 1 ? lin signal to lef t mixer enable li2lovol 5:3 lin signal to left mixer gain 000 ? 6 db 001 ? 3 db 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) 6.3.18 register 40 ? dac control 18 , default 0010 1000 bit name bit description 6.3.19 register 41 ? dac control 19 , default 0010 1000 bit name bit description 6.3.20 register 42 ? dac control 20 , default 0011 1000 bit name bit description rd2ro 7 0 ? right dac to right mixer disable (default)
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 27 1 ? right dac to right mixer enable ri2ro 6 0 ? rin signal to r ight mixer disable (default) 1 ? rin signal to right mixer enable ri2rovol 5:3 rin signal to right mixer gain 000 ? 6 db 001 ? 3 db 010 ? 0 db 011 ? - 3 db 100 ? - 6 db 101 ? - 9 db 110 ? - 12 db 111 ? - 15 db (default) 6.3.21 register 43 ? dac control 21 , default 0000 0 000 bit name bit description slrck 7 0 ? daclrc and adclrc separate (default) 1 ? daclrc and adclrc same lrck_sel 6 master mode, if slrck = 1 then 0 ? use dac lrck (default) 1 ? use adc lrck offset_dis 5 0 ? disable offset (default) 1 ? enable of fset mclk_dis 4 0 ? normal (default) 1 ? disable mclk input from pad adc_dll_pwd 3 0 ? normal (default) 1 ? adc dll power down dac_dll_pwd 2 0 ? normal (default) 1 ? dac dll power down 6.3.22 register 44 ? dac control 22 , default 0000 0 000 bit name bit desc ription offset 7:0 dc offset 6.3.23 register 45 ? dac control 23 , default 0000 0000 bit name bit description vroi 4 0 ? 1.5k vref to analog output resistance (default) 1 ? 40k vref to analog output resistance 6.3.24 register 46 ? dac control 24 , default 0000 0000 bit name bit description lout1vol 5 :0 lout1 volume 000000 ? - 45 db (default) 000001 ? - 43.5 db
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 28 000010 ? - 42db ? 011110 ? 0 db 011111 ? 1 .5 db ? 10000 1 ? 4.5 db 6.3.25 register 47 ? dac control 25 , default 0000 0000 bit name bit description rout1vol 5 :0 rout1 vo lume 000000 ? - 45 db (default) 000001 ? - 43.5 db 000010 ? - 42db ? 011110 ? 0 db 011111 ? 1 .5 db ? 10000 1 ? 4.5 db 6.3.26 register 48 ? dac control 26 , default 0000 0000 bit name bit description lout2vol 5 :0 lout2 volume 000000 ? - 45 db (default) 000001 ? - 43.5 db 00 0010 ? - 42db ? 011110 ? 0 db 011111 ? 1 .5 db ? 10000 1 ? 4.5 db 6.3.27 register 49 ? dac control 27 , default 0000 0000 bit name bit description rout2vol 5 :0 rout2 volume 000000 ? - 45 db (default) 000001 ? - 43.5 db 000010 ? - 42db ? 011110 ? 0 db 011111 ? 1 .5 db ? 1000 0 1 ? 4.5 db
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 29 6.3.28 register 50 ? dac control 28 , default 0000 0000 bit name bit description 6.3.29 register 51 ? dac control 29 , default 1 0 1 0 1 0 1 0 bit name bit description hplout1_ref1 7 reserved hplout1_ref2 6 reserved 6.3.30 register 52 ? dac control 30 , default 1 0 1 0 1 0 1 0 bit name bit description spklout2_ref1 7 reserved spklout2_ref2 6 reserved mixer_ref1 3 reserved mixer_ref2 2 reserved mref1 1 reserved mref2 0 reserved 7 d igital audio interface the device provides four formats of serial audio data interface to the input of the dac or output from the adc through lrck, sclk and sd in/sdout pins. the four formats are i 2 s, left justified, right justified and dsp/pcm mode. dac input dsdin is sampled by ES8388 on the rising edge of dsclk. adc data is out on asdout and changes on the falling edge of asclk. the relationship of sdata ( sd in/sdout) , sclk and lrck with the three formats is shown through figure 3 to figure 7. n-2 n-1 n 3 2 1 1 sclk msb lsb left channel n-2 n-1 n 3 2 1 1 sclk msb lsb right channel sdata sclk lrck figure 3 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 4 left justified serial audio data format up to 24 - bit
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 30 n-2 n-1 n 3 2 1 msb lsb left channel n-2 n-1 n 3 2 1 msb lsb right channel sdata sclk lrck figure 5 right justified serial audio data format up to 24 - bit figure 6 dsp /pcm mode a figure 7 dsp /pcm mode b 8 electrical character istics 8.1 ab solute maximum ratings continuous operation at or beyond these condition s may permanent ly damage the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0.3v +5.0v input voltage range dgnd - 0.3v dvdd+0.3v oper ating temperature range - 40 c +85 c storage temperature - 65 c +150 c
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 31 8.2 recommended operating conditions parameter min typ max unit analog supply voltage level 1.7 3.3 3.6 v digital supply voltage level 1.5 1.8 3.6 v 8.3 adc analog and filter characteristics and specifications test condition s are as the following unless otherwise specify: avdd=+ 3 . 3 v, dvdd=+ 1 . 8 v, agnd=0v, dgnd=0v, ambient temperature=+25 c , fs=48 khz , 96 khz or 192 khz , mclk/lrck=256. parameter min typ max unit a d c performance dynamic range (note 1) 85 95 98 db thd + n - 88 - 85 - 75 db channel separation (1khz) 80 85 90 db sign al to noise ratio 85 95 98 db interchannel gain mismatch 0.1 db gain error 5 % filter frequency response ? single speed passband 0 0.45 35 fs stopband 0.54 65 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response ? double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/ 3.3 vrms input impedance 20 k ? note 1. the value is measured used a - weighted filter. 8.4 dac analog and filter characteristics and specifications test condition s are as the following unless otherwise specify: avdd=+ 3 . 3 v, dvdd=+ 1 . 8 v, agnd=0v, dgnd=0v, ambient temperature=+25 c , fs=48 khz , 96 khz or 192 khz , mclk/lrck=256. parameter min typ max unit dac performance dynamic range (note 1) 83 96 98 db thd + n - 85 - 83 - 75 db channel separation (1khz) 80 85 90 db
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 32 sign al to noise ratio 83 96 98 db interchannel gain m ismatch 0. 0 5 db filte r frequency response ? single speed passband 0 0.45 35 fs stopband 0.54 65 fs passband ripple 0.05 db stopband attenuation 40 db filter frequency response ? double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 40 db de - emphasis error at 1 khz (single speed mode only) fs = 32khz fs = 44.1khz fs = 48khz 0.002 0.013 0.0009 db analog output full scale output level avdd/3.3 vrms note 1. the value is measured used a - weighted filter. 8.5 power consumption characteristics parameter min typ max unit normal operation mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v: play back play back and record dvdd=3.3v, pvdd=3.3v, avdd=3.3v: play back play back and record 7 16 31 59 m w power down mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v dvdd=3.3v, pvdd=3.3v, avdd=3.3v 0.3 1.9 m w 8.6 serial audio port switching specifications parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low t sclkl 15 ns sclk pulse width high t sclkh 15 ns
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 33 sclk falling to lrck edge t slr C10 10 ns sclk falling to sdout valid t sdo 0 ns sdin valid to sclk rising setup time t sdis 10 ns sclk rising to sdin hold time t sdih 10 ns figure 8 serial audio port timing
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 34 8.7 serial control port switching specifications parameter symbol min max unit spi mode spi_clk clock frequency 10 mhz spi_clk edge to spi_csn falling t spics 5 ns spi_csn high time between transmissions t spish 500 ns spi_csn f alling to spi_clk edge t spisc 10 ns spi_clk low time t spicl 45 ns spi_clk high time t spich 45 ns spi_din to spi_clk rising setup time t spids 10 ns spi_clk rising to data hold time t spidh 15 ns 2 - wire mode scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 n s sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 n s fall time scl t twf 300 ns spi_din spi_clk spi_csn t spics t spisc t spids t spidh t spich t spicl t spish s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 serial control port 2 - wire timing figure 9 serial control port spi timing
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 35 9 package information
everest semiconductor ES8388 revision 5 .0 july 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 36 10 corpoaration information everest semiconductor co., ltd. ??? 328 ?????? 6a ? 215028 email: info@everest - semi.com

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